[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Oct 9 15:38:51 BST 2020


--- Comment #45 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #44)

> then how are Rc=1 operations treated?

remember, jacob, unlike e.g. RISCV which can only do conditional test/branch
through BEQ/BNE, PowerISA had these Rc=1 modes which test the arithmetic
result.  the logic gates needed to do so is quite small so is easily
justifiable, when you get a "free eq/gt/lt" comparison as part of every
arithmetic op.

it would be anomalous to only modify cmp to become a single-bit comparison:
questions would be asked by experienced (puzzled) PowerISA architects, "why on
earth are you proposing cmp be reduced in capability to single bit instead of a
full CR in the first place, and why only cmp rather than all Rc=1 operations?"

we have to be able to justify that to people with *25* years experience in
PowerISA and i definitely don't have good answers, additionally being instead
much more in favour of respecting PowerISA scalar capability (Rc=1 included)
just extended to the parallel domain.  (general rule of SV: don't change the
scalar behaviour without a damn good reason)

if however predicates must be *applied* via bitwise (from INT GPRs) then
popcount (etc) gets a word in edgeways.

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