[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Oct 8 01:19:25 BST 2020


--- Comment #34 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #33)
> (In reply to Jacob Lifshay from comment #32)
> > My comments on jitsi call:
> > what about redirecting cr* to integer registers for vector compares?
> interesting thought.. ah wait so instead of the CR going into an actual CR
> it gies directly into an int regfile?
> so sort-of an implicit vector-mcrf?
> my concern with that idea although it gas merit in that we would not need to
> expand CR to 64 entries is, it kinda breaks the way PowerISA works.
> it does have advantages so let's add it to the list of options, comparing it
> against simply "vectorising mcrf".
> the reason for that being, CR operations are designed to operate at the
> bitlevel where INT operations are not.

the idea is that the compare would produce 1 bit per vector lane and
essentially directly generate a predicate mask into an integer register. For
that to work, the compare would need extra bits (normally in the branch
instruction for scalar powerpc) to know which of lt, le, eq, ne, etc. it should
use, those bits come from the prefix.

As long as it's one bit per lane, scalar integer ops are even better than cr
ops for the required bit manipulations.

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