[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #91 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
just some notes (which i will edit into comment 0 later) it took a while to
explain the various different predication ideas, however at the end of it Paul
came up with a crucial insight:

that whatever we propose to OpenPOWER for inclusion in the ISA, if it is
complex, it also has to show a corresponding increase in benefit.

i.e. if it is simpler, the "justification barrier" will be less.

i think this is very important to add to each proposal for predication, here. 
i have not-exactly done that but not explicitly.

my point being, Jacob, that, leaving micro-architectural implementation details
entirely aside: to modify the OpenPOWER ISA (drop CRs when vectorised for
example) has to have a clear and substantially compelling case for doing so
when compared to the much simpler case of element-stratified vectorisation of
CRs, respecting the principle that SV is a "hardware for-loop around
essentially unmodified *scalar* pipelines"

XER.SO on the other hand is so disastrous to parallelism that it is easy to
justify not supporting it at all in SV Mode

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