[Libre-soc-dev] daily kan-ban update 24sep2022

lkcl luke.leighton at gmail.com
Sat Sep 24 11:51:44 BST 2022

they are subtly different when it comes to bit-slip detection, this is phase-adjustment from reading the 4 places on the incoming signals, 0 90 180 270, DDR signals are often not properly synced and you have to add manual phase delay.


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