luke.leighton at gmail.com
Wed Sep 14 12:18:27 BST 2022
the epic saga on pack/unpack continues.
extending setvl with additional bits by leveraging the
24 bits as "extra arguments" is in effect embedding
a 64-bit *scalar* instruction into the Vector-Loop space.
this was illustrated by me attempting to create an exception
for the loop-enabling in ISACaller.
as in: when doing sv.setvl the simulator actually tried to do
a for-loop around "setvl"!
we therefore either need v3.1 EXT001 Prefixed setvl (psetvl)
or to add a secondary "svmgmt" instruction to set the two
pack/unpack bits in SVSTATE.
madness. just to add pack/unpack.
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