[Libre-soc-dev] Orangecrab progress
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Sep 12 21:18:48 BST 2022
On Mon, Sep 12, 2022 at 9:10 PM Tobias Platen via Libre-soc-dev
<libre-soc-dev at lists.libre-soc.org> wrote:
> I tried to get a uart output in icarus verilog, that did not work for
> an unknown reason. Knowing that the uart works in ls2 and that the core
> boots from the right location, I flashed the orangecrab with the latest
> version of ls2. As expected it shows the Soc features,
> but DRAM fails:
> Soc signature: 00010001F00DAA55 Soc features: UART DRAM
> Auto calibration profile:p0 rdly:00000007 p1 rdly:00000007
> Reloading built-in calibration profile...DRAM test...
yyep, this is "normal" and needs a lot of experimentation
and investigation. each time i try to sort this out it takes
weeks - full-time - and i can't afford to do that.
Cesar may be able to help, he has one of the orangecrabs.
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