luke.leighton at gmail.com
Sat Oct 22 18:19:00 BST 2022
today i tried making dsld/dsrd 4-operand. it went really well,
right up to the point i ran the bigint vector tests at which point
it all went to shit.
4-op is EXTRA2 which in this case prohibits specifying a pair
of operands for consecutive HI-LO operand selection as to
the 128-bit source to be shifted.
the only workaround is to either use svoffset or take a copy
of the entire source vector in order to shift the HI source up
by one register.
for elwidth overrides that actually will have to be done (copy
or svoffset) which begs the question: is it worthwhile to have
some form of special (non-orthogonal) behaviour involving
RC and the 9th bit of EXTRA which is free in EXTRA2 4-operand
or, to attempt 3-operand EXTRA3 with 4 operands, treating the
shift source as mandatory scalar, for example?
several possibilities, none of them good ones.
More information about the Libre-soc-dev