[Libre-soc-dev] daily kan-ban update 11mar2022

[Boris Shingarov]

Tobias,

> I got microwatt and the external UART working, next I'll do the maze
> game.

Ecstatic!

How did you solve the problem with DDR3 not working?  the one where odd 
bytes arrive one cycle behind?

Background: about six months ago I followed Jeremy and Matt's steps from 
the "Little guide to building & running Microwatt + Linux on OrangeCrab" 
and found that the DRAM does not work. Jeremy confirms he can reproduce 
the problem.  For saving the conversation in a non-private medium, I am 
reprinting it here:

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Boris Shingarov> @Jeremy Kerr , @Matt Johnston:

Boris Shingarov> > little guide to building & running Microwatt + Linux 
on OrangeCrab

Boris Shingarov> I just tried reproducing these steps on my OC F85.  I 
noticed two problems.
Boris Shingarov> First, in the UART connection diagram in the guide, the 
TX and RX are reversed, at least with the current head of the gateware 
IO0 is the Crab's TX and IO1 is the Crab's RX.
Boris Shingarov> The second problem seems to be something deeper: for 
some reason the DRAM does not work:

Welcome to Microwatt !

  Soc signature: f00daa5500010001
   Soc features: UART DRAM SPIFLASH SDCARD
           DRAM: 256 MB
      DRAM INIT: 8 KB
            CLK: 48 MHz
   SPI FLASH ID: ef4018
  SPI FLASH OFF: 0x400000 bytes

LiteDRAM built from Migen -------- and LiteX --------
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
   m0, b00: |01110000| delays: 02+-01
   m0, b01: |00000000| delays: -
   m0, b02: |00000000| delays: -
   m0, b03: |00000000| delays: -
   best: m0, b00 delays: 02+-01
   m1, b00: |01110000| delays: 02+-01
   m1, b01: |00000000| delays: -
   m1, b02: |00000000| delays: -
   m1, b03: |00000000| delays: -
   best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
   Write: 0x40000000-0x40200000 2.0MiB
    Read: 0x40000000-0x40200000 2.0MiB
   bus errors:  1/256
   addr errors: 32/8192
   data errors: 524279/524288
Memtest KO
Trying flash...
Copy segment 0 (0x4dbe9a bytes) to 0x1500000
Booting from DRAM at 1500000

Jeremy Kerr> @Boris Shingarov ok, I'll check out the UART connections 
there. Looks like memtest is failing though, which may be 
hardware-specific. We have one board that passes, one that fails in the 
same way as yours there.
Jeremy Kerr> (we're looking into it though!)

Jeremy Kerr> getting some interesting memtest failures

memtest_data error @ 0x40000000: 0xb320bd03 vs 0x80200003
memtest_data error @ 0x40000004: 0x80300002 vs 0xc0300002
memtest_data error @ 0x40000008: 0xc0180001 vs 0x60180001
memtest_data error @ 0x4000000c: 0x602c0003 vs 0xb02c0003
memtest_data error @ 0x40000010: 0xb0360002 vs 0xd8360002

Jeremy Kerr> looks like the odd bytes are one "cycle" behind

lkcl> jeremy: intriguing. what's the context? ECP5? Arty-A7? Verilator 
simulation? is that DRAM (DDR3) or SDRAM1?

Matt Johnston> lkcl: orangecrab, so ecp5 with ddr3. running 48mhz, 
though 55mhz was similar

lkcl> does it also occur under verilator-simulation?

lkcl> the reason i ask is for triaging which side of the LD/ST wishbone 
interface it is (i.e. in microwatt, or in the PHY)

lkcl> although, i did see things like this when getting the DRAM timing 
params not quite right

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So at this point, from a sheer Justus von Liebig perspective, we can't 
claim that "microwatt works on OC"; only that "microwatt exhibits 
interesting DRAM irregularities on OC".  Has there been an update on 
this?  did I sleep through it?