[Libre-soc-dev] Reservation Stations. Was [Libre-soc-bugs] [Bug 782] add galois field bitmanip instructions

[lkcl]

actually, sorry: it's much "worse" than it seems.  let us assume you have
a loop which is executed 500 times and contains an instruction which
takes 500 cycles (remember, it is completely irrelevant whether it
is a FSM or a pipeline)

after 500 cycles you will have 500 of those instructions outstanding
in the [500] RSes.

however when moving on to the code *outside* of the loop, if there
is any dependence on the data still in the [500] operations caused
by the loop, then you had damn well better have 500 RSes for
*those* instructions as well.

loop:
        500op r0, r0, r0
        bc loop
        add r0, r0, r0
        mul r1, r2, r0
        sub r0, r1, r0
        ...
        ...
        ; 500 other instructions using r0

if you do not want the above program to stall, then there must
be not only 500 RSes for the 500op instruction, you MUST also
have 500 RSes for add, mul and sub as well, and any other
instruction that uses r0.

this should start to go a long way towards understanding why
modern out-of-order multi-issue processors (POWER10, AMD,
Intel) have a THOUSAND Reservation Stations.

l.