[Libre-soc-dev] Reservation Stations. Was [Libre-soc-bugs] [Bug 782] add galois field bitmanip instructions

[Jacob Lifshay]

Ok, it turns out that I likely got my terms mixed up, in the bugzilla
messages I kept using FU but instead meant a RS.

On Tue, Mar 8, 2022, 04:47 lkcl <luke.leighton at gmail.com> wrote:

>
> FSMs that take say 30 cycles (and therefore require a minimum
> of 30 Reservation Stations)


why in the world would you need 30 RSes?! if the FSM starts 1 instruction,
executes for 30 cycles, and then can start the next instruction (i'm
assuming it can't run multiple instructions simultaneously in the FSM),
there only needs to be enough RSes to ensure that it can always start
executing the next instruction immediately when it finishes the previous
instruction. for a FSM that slow, you could probably get away with only 2
RSes, since the non-executing RS would write its results to registers or
wherever, finish, and a new instruction would be placed in the RS before
the FSM finished, once the FSM finished, it would just swap which RS was
executing and which had finished executing.

>that's kinda deceptive, since the muxes with the massive fan-out/in are
> >now in
> >the scheduler logic and the busses for carrying intermediate register
> >values
> >around (i temporarily forgot the name) rather than in the pipeline
> >fan-in
> >fan-out.
>
> no, it's not [deceptive], and they're not [in the scheduler logic].
> you probably mean PriorityPickers and CDBs (see further below)
> in which case you've conflated two different mux-buses
>

i'm abusing notation when I wrote "scheduler logic", by that I meant all
the rest of the cpu that is responsible for moving data between RS outputs
and other RS inputs.

>
> the fundamental rule is that you absolutely cannot have untracked
> resources. period.  this is non-negotiable.
>

yeah, i never claimed to have untracked instructions or untracked
structural constraints.

so, before getting on to the paragraphs below, let me state:
>
> 1)  if you have a 10-stage pipeline or a 10-stage FSM, it is the
>    *completion* time that matters (10 clocks) NOT whether it is
>    a pipeline or a FSM, you ABSOLUTELY MUST have an
>    absolute bare minimum of 10 Reservation Stations
>

I disagree, it's the minimum number of instructions in flight needed to
avoid unnecessary stalls that dictate RS counts, not completion time.
you're over-generalizing from how many RSes you need for pipelining. If you
can only execute 1 instruction at a time in a given FSM/pipeline, you only
need enough RSes to keep it fed, even if it takes 500 cycles to execute
that instruction. at least one RS must be ready to execute immediately when
the FSM can start executing again, at any other time you can have 0 ready
RSes. You do not need 500 RSes there.

I trimmed the rest of the email since I read it but have no particular
response...mentioning this to avoid you feeling like i ignored you.

Jacob