[Libre-soc-dev] daily kan-ban update 01mar2022

[Tobias Platen]

Today: trying to build microwatt for orangecrab, which fails.
this time on my laptop, which has a known working toolchain for
microwatt-verilator.

10. Executing Verilog-2005 frontend: uart16550/uart_wb.v
Parsing Verilog input from `uart16550/uart_wb.v' to AST representation.
Storing AST representation for module `$abstract\uart_wb'.
Successfully finished Verilog frontend.

-- Running command `ghdl --std=08 --no-formal -gMEMORY_SIZE=8192 -
gRAM_INIT_FILE=hello_world/hello_world.hex -gRESET_LOW= -gCLK_INPUT= -
gCLK_FREQUENCY= decode_types.vhdl common.vhdl wishbone_types.vhdl
fetch1.vhdl utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl
decode1.vhdl helpers.vhdl insn_helpers.vhdl control.vhdl decode2.vhdl
register_file.vhdl cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl
rotator.vhdl logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl
execute1.vhdl loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl
core_debug.vhdl core.vhdl fpu.vhdl wishbone_arbiter.vhdl
wishbone_bram_wrapper.vhdl sync_fifo.vhdl wishbone_debug_master.vhdl
xics.vhdl syscon.vhdl soc.vhdl spi_rxtx.vhdl spi_flash_ctrl.vhdl
fpga/soc_reset.vhdl fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd
fpga/main_bram.vhdl nonrandom.vhdl fpga/clk_gen_ecp5.vhd fpga/top-
generic.vhdl dmi_dtm_dummy.vhdl -e toplevel; read_verilog
uart16550/raminfr.v uart16550/uart_defines.v uart16550/uart_receiver.v
uart16550/uart_regs.v uart16550/uart_rfifo.v
uart16550/uart_sync_flops.v uart16550/uart_tfifo.v uart16550/uart_top.v
uart16550/uart_transmitter.v uart16550/uart_wb.v ; synth_ecp5 -json
microwatt.json  ' --

11. Executing GHDL.
error: missing value in generic override option

yosys --version
Yosys 0.13+10 (git sha1 36482680d, clang 11.0.1-2 -fPIC -Os)

ghdl --version
GHDL 2.0.0-dev (1.0.0.r974.g0e46300c) [Dunoon edition]