[Libre-soc-dev] L1 Cache, MMU, Load/Store status

[lkcl]

On January 30, 2022 6:44:42 PM UTC, Tobias Platen <libre-soc at platen-software.de> wrote:
>This looks good.
>Since I don't have an ECP5 I will continue simulating with verilator.

using nmigen Memory, verilator of Libre-SOC is now 1.5x faster than microwatt, that is without the in-order core, but i have no idea if it would be faster or slower.

it will still take 2 hours to get to the boot prompt but that is still better than 60 hours.

l.