[Libre-soc-dev] L1 Cache, MMU, Load/Store status

lkcl luke.leighton at gmail.com
Sun Jan 30 17:15:16 GMT 2022

these now seem functional, having passed the former segfault point due to misaligned stores corrupting.

i have just tried compiling synth_ecp5 and was stunned to encounter my laptop with 64 GB RAM going into swapspace.

investigation showed that the L1 CacheRAMs were done as DFFs which consumed vast resources.  conversion of CacheRAM to nmigen Memory not only fixed that but caused a massive 15x speedup of verilator simulations.

it may now only take 3 hours to get to the buildroot linux-5.7 boot prompt.

i will now begin investigating compiling for ECP5.  initial unoptimised LUT4 resource utilisation is 80k LUT4s but that is before BRAM allocation.

a LOT of work still to be done.


More information about the Libre-soc-dev mailing list