[Libre-soc-dev] daily kan-ban update 21jan2022

Tobias Platen libre-soc at platen-software.de
Fri Jan 21 18:34:26 GMT 2022

today: installed yosys, ghdl and ghdl-yosys-plugin in a chroot

in microwatt when I run make, I got the following error:

cc -O3 -Wall   -c -o sim_vhpi_c.o sim_vhpi_c.c
cc -O3 -Wall   -c -o sim_bram_helpers_c.o sim_bram_helpers_c.c
cc -O3 -Wall   -c -o sim_console_c.o sim_console_c.c
cc -O3 -Wall   -c -o sim_jtag_socket_c.o sim_jtag_socket_c.c
ghdl -i --std=08 --work=unisim --workdir=sim-unisim sim-
unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl sim-
ghdl -c --std=08 -Psim-unisim -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o
-Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o decode_types.vhdl
common.vhdl wishbone_types.vhdl fetch1.vhdl utils.vhdl plru.vhdl
cache_ram.vhdl icache.vhdl decode1.vhdl helpers.vhdl insn_helpers.vhdl
control.vhdl decode2.vhdl register_file.vhdl cr_file.vhdl
crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl logical.vhdl
countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl loadstore1.vhdl
mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl core.vhdl fpu.vhdl
pmu.vhdl wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl
sync_fifo.vhdl wishbone_debug_master.vhdl xics.vhdl syscon.vhdl
gpio.vhdl soc.vhdl spi_rxtx.vhdl spi_flash_ctrl.vhdl sim_console.vhdl
sim_pp_uart.vhdl sim_bram_helpers.vhdl sim_bram.vhdl
sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl
sim_16550_uart.vhdl foreign_random.vhdl glibc_random.vhdl
glibc_random_helpers.vhdl core_tb.vhdl -e core_tb

ghdl:error: unknown warning identifier: l,sim_vhpi_c.o

Is there any script to converte microwatt to verilog?

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