[Libre-soc-dev] [OpenPOWER-HDL-Cores] microwatt dcache potential bug (overlap r0 and r1)
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat Jan 15 21:06:27 GMT 2022
On Sat, Jan 15, 2022 at 11:32 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> > Notice you have r1.req.op there whereas the VHDL has req.op. I think
> > that's your bug. (Similarly line 1560 has r1.req.dcbz not req.dcbz,
> > and line 1559 has r1.req.same_tag not req.same_tag.)
overlapping development of LR/SC with testing this (keeping
the r1_next_full flag though), works great. can clearly see a
reduction in the number of cycles taken by about... 5%.
oh and no instructions lost.
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