[Libre-soc-dev] microwatt dcache potential bug (overlap r0 and r1)
luke.leighton at gmail.com
Thu Jan 13 16:59:13 GMT 2022
on further investigation i realised that neither correction to RELOAD_ACK_WAIT nor the store equivalent is correct... yet neither is the existing HDL.
setting r1.full=0 early (the current code) would seem like the right thing to do but leaves ACKs outstanding that merge with and interfere with future operations.
not setting r1.full at these early-answer points causes acks_pending to get out of sync, with catastrophic consequences.
i am very much floundering about, here. what i will try next is to terminate further requests (limit acks_pending to 1 or 0) when a new incoming request is made by r0, but only do so when r1.full=1
the hope there is that stopping speculative acks will stop the cross-interference, but that by checking r1.full it is using it to make sure that the *non*-speculative request is actually served.
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