[Libre-soc-dev] VERSA_ECP5 with DDR3 on nmigen ls2.py at 50 mhz
luke.leighton at gmail.com
Sat Feb 19 12:22:46 GMT 2022
the goal here is to reach 50 mhz for an FPGA build so that it is
possible to run linux 5.7
ls2.py, a new nmigen-based general-purpose Power ISA peripheral
fabric, is designed for accepting any external core that has 64 bit
wishbone and a DMI interface, therefore both microwatt and libre-soc
can be used.
with the new ls2.py peripheral fabric i have successfully managed to
cut the caches down small enough and found the parameters needed such
that the following worked:
* nmigen-based DDR3 PHY called "gram"
* opencores uart16550
* drastically cut down dcache and icache
* a 50 mhz clock rate
this resulted in a 95% TRELLIS_SLICE utilisation, a predicted 43 mhz
"fail" report on timing by nextpnr-ecp5 but an actual success when
actually run at 50 mhz.
it is an extremely important intermediary step because unless 50 mhz
is achieved the DRAM IC will not initialise (and, as explained
previously, sys_clk === dram_clk in all other Libre/Open peripheral
fabrics at the moment)
tomorrow's task therefore will be to put together some bare metal cold
boot firmware using a combination of microwatt ppc64 helloworld, the
microwatt sdram_init.c program, and the gram DDR3 c source code
previously only ever tested for Minerva RV32I.
in essence libdram and litedram can be cut out entirely, there will be
once the DRAM is confirmed functional the next step will be to drop in
an SPI core (which had better be damn small, the limits are being
pushed here for the VERSA_ECP5) and attempt to read and then execute
from the SPI Flash.
at that point it will be possible to attempt a linux 5.7 boot.
the number of cache lines and TLB sizes had to be cut back
drastically, they take up considerable resources unfortunately. this
means changing the corresponding microwatt.dts settings which is fine.
More information about the Libre-soc-dev