[Libre-soc-dev] effect of more decode pipe stages on hardware requirements for execution resources for OoO processors
Jacob Lifshay
programmerjake at gmail.com
Wed Feb 16 16:34:09 GMT 2022
On Wed, Feb 16, 2022, 02:32 lkcl <luke.leighton at gmail.com> wrote:
> On Wed, Feb 16, 2022 at 6:02 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> let us start again.
>
Ok.
>
> let us use mathematical notation
>
> "For the infinite set of all possible instruction sequences, there
> exists a sequence of 40 instructions such that there are 39 RaW-WaR
> hazards between each pair in sequence such that 40 RSes *are* required
> to hold the full chain"
>
> let us call that Chain40
>
> the *actual* instructions within Chain40 are completely irrelevant.
> it is the fact that there *is* a chain that is the sole exclusive
> critical fact. please do not place or create barriers or argue with
> the fact that such a chain exists, nor argue or advocate any
> additional circumstances which make Chain40 a non-possibility.
>
> now let us also create some additional groups:
>
> "For the infinite set of all possible instruction sequences, there
> exists 40 instruction sequences of length 1 (one), such that they have
> no Hazards at all onto Chain40 *and* have no Hazards with each other"
>
> let us call those NonChain1-40
>
> so:
>
> * there are 40 instructions in a chain of 39 hazards with each other,
> called Chain40
> * there are 40 instructions with *no* Hazards either on each other or
> with Chain40, called NonChain40
>
> now let us define the hardware:
>
> * let the pipeline depth be 2 for ALL instructions
> * let the instructions to be executed be: Chain40 followed by
> NonChain1...NonChain40
> * let us assume 100-way multi-issue (please do not argue that this is
> impractical at this point in time)
>
> QUESTION: how many Reservation Stations are required to ensure that an
> issue-stall does not occur?
>
that depends on what you mean by pipeline depth...which pipeline(s)? how is
it distributed? is it 2 cycles for every execution pipeline and 0 cycles in
the fetch/decode pipeline? is it 1 cycle for every execution pipeline and 1
cycle in the fetch/decode pipeline? is it 2 cycles in the fetch/decode
pipeline and 1 cycle in every execution pipeline?
>
> now let us change one parameter:
>
> * let the pipeline depth increase to 10
>
> QUESTION: what effect does this have on the number of Reservation
> Stations required?
>
that depends on what you mean by pipeline depth...which pipeline(s)? if
it's the fetch/decode pipeline only that is increasing in depth, then
exactly the same number of RSes are needed. if execution pipelines also
increase in depth, then more RSes may be needed, dependent only on the
fetch width in instructions and the execution pipelines' depth and other
factors (that we're assuming don't occur here) that cause instructions to
be delayed in the execution or scheduling stages (we're assuming scheduling
takes 0 cycles if there's no stall), such as running out of RSes or
insufficient execution pipelines or stalled instructions (e.g. tlb miss in
a load/store).
Jacob
More information about the Libre-soc-dev
mailing list