[Libre-soc-dev] effect of more decode pipe stages on hardware requirements for execution resources for OoO processors
luke.leighton at gmail.com
Wed Feb 16 03:01:48 GMT 2022
On February 16, 2022 2:44:34 AM UTC, Jacob Lifshay <programmerjake at gmail.com> wrote:
>that's kinda unreasonable -- every cpu in existence has to respect RAW
>dependencies cuz that's how instructions transfer data to other
>instructions through registers.
the purpose of the exercise is precisely and exactly to create a massive logjam of RaW and WaR hazards (that are 100% satisfiable without cancellation) of at least 40+ instructions, all dependent on each other.
then to increase the number of pipeline stages and see how many extra Reservation Stations are required in order to allow the exact same instructions to be in-flight without an issue stall.
it should be pretty obvious that even in a single issue scenario if you have an instruction that requires 128 cycles to complete (e.g. a DIV) you clearly need more than 128 Reservation Stations in order to avoid an issue stall.
it should also be obvious that if the decode phase increases by say 10 cycles, that now more than 10+128 Reservation Stations are required to prevent an issue stall.
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