[Libre-soc-dev] effect of more decode pipe stages on hardware requirements for execution resources for OoO processors

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Feb 16 02:02:04 GMT 2022

On Wed, Feb 16, 2022 at 1:09 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> making it 8-wide exposes the loop-carried dependencies on ctr and the
> address in r3, making the loop max out at 4 instructions per cycle despite
> the larger fetch bandwidth.

assume that the LDs and STs are independent such that there is no such
limit [like in the score6600_multi.py LDST address hazard detector]


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