[Libre-soc-dev] core with L1 Cache and MMU booting on VERSA_ECP5

lkcl luke.leighton at gmail.com
Wed Feb 2 00:43:28 GMT 2022

running with a basic BIOS i can confirm that the latest libre-soc core is operational, at least with real mode memory.

the next task will be to create a suite of peripherals most likely using a combination of lambdasoc, jean thom's DDR3 PHY/Controller, uart16550 from opencores, and any SPI PHY i can find.


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