[Libre-soc-dev] Coriolis 2 - Tutorials and check

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Sun, Aug 14, 2022 at 4:40 AM Santhosh Kumar V V . via Libre-soc-dev
<libre-soc-dev at lists.libre-soc.org> wrote:
>
> Sir I tried running the git version as mentioned all the folders are set to
> the given version.

ok brilliant.

> (coriolis)santhosh at vvsdebian:~/alliance$ git reset --hard
> c12f377989571c1d868bebebdfb1574572e2ccf9
> HEAD is now at c12f3779 Support for longer lines in the Ap parser (up to
> 2048 characters).

now remember you must rebuild alliance, see section 3.1
https://libre-soc.org/HDL_workflow/coriolis2/

> (coriolis)santhosh at vvsdebian:~/coriolis-2.x/src/coriolis$ git reset --hard
> f1668cec5f6ae3ad2b6fea07ba11654d6a8db370
> Checking out files: 100% (8501/8501), done.
> HEAD is now at f1668cec Disable BFD support by default.

actually i apologise you should have this tag:
https://gitlab.lip6.fr/vlsi-eda/coriolis/-/tree/LS180_RC7_FINAL

see line 69 here:
https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=coriolis-install;h=d148371367d313281e985b3453040128cadb53d8;hb=bae2009ffc5a3aa630990943abc825585f6927ae#l69

you *may* not need to rebuild coriolis2 because the tag is
(within reason) the correct one.

> I tried running buil_full_4ksram.sh but still the same error is displayed.
>
> [ERROR] CParsVst() VHDL Parser - File:<./cmpt_sram4k_0.vst> Line:418
>         Port map assignment discrepency instance:0 vs. model:1
>         Model: "vdd"
>         Instance:
>         Python stack trace:
>         #0 in                scriptMain() at doDesign.py:36

yes if you have not rebuilt alliance, it is no good running the same
command with the same binary executables, you will of course get
the same results.

l.