[Libre-soc-dev] [SVP64] feedback needed - Pack/Unpack (vpack/vunpack)

[lkcl]

drat.

https://libre-soc.org/openpower/sv/svp64/#index12h1

predicate mask (3 bits) not.elwidth (2 bits).


currently fmv (etc) are RM-2P-1S1D with EXTRA3.
3bit extra3 src
3bit extra3 dat
3bit dest predicate

all 9 bits of EXTRA taken up.

no room to do trick of using 1 bit to reinterpret elwidth bits
as P/U.

annoyingly.  it would work well.

sacrificing twin predication not really an option.  also too close
to RFC submission to do major redesigns esp. with resource
commitment on spec, sim, HDL, tests, binutils.

l.