[Libre-soc-dev] Coriolis 2 - Tutorials and check
Santhosh Kumar V V .
123040015 at sastra.ac.in
Wed Aug 10 12:52:00 BST 2022
I'll try to run that.
On Wed, Aug 10, 2022 at 3:28 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
wrote:
> On Tue, 2022-08-09 at 22:52 -0400, Santhosh Kumar V V . via Libre-soc-dev
> wrote:
> > I tried running the codes as you instructed it works fine Now
> > *I can see the chip_r in cgt.*
> > I proceeded with the same instructions to make /build_full_4ksram.sh
> >
> > They are showing some errors.
> >
> > Traceback (most recent call last):
> > File "/home/santhosh/alliance-check-toolkit/bin/yosys.py", line 8, in
> > <module>
> > from helpers.io import ErrorMessage
> > File
> >
> "/home/santhosh/coriolis-2.x/Linux.x86_64/Release.Shared/install/lib64/python2.7/dist-packages/crlcore/helpers/__init__.py",
> > line 101
> > print textStackTrace( trace, True )
> > ^
> > SyntaxError: invalid syntax
> > make: *** [mk/synthesis-yosys.mk:53: ls180.blif] Error 1
>
> Hello,
>
> What's wrong here is that you have a Coriolis2 version build over
> Python 2.7 (as the path clearly shows), but most likely, you try
> to run the script with a Python 3 interpreter (hence the error
> due to the change of syntax of the print function).
>
> Best,
> --
> .-. J e a n - P a u l C h a p u t / Administrateur Systeme
> /v\ Jean-Paul.Chaput at lip6.fr
> /(___)\ work: (33) 01.44.27.53.99
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>
> S U Sorbonne Université (former UPMC)
> L I P 6 Laboratoire d'Informatique de Paris VI
> C I A N Circuits Intégrés Analogiques & Numériques
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>
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