[Libre-soc-dev] svp64 review and "FlexiVec" alternative

[lkcl]

On Wed, Aug 3, 2022 at 10:31 PM Jacob Bachmeyer <jcb62281 at gmail.com> wrote:

> Why would that same parallel tree reduction mode (invisibly selected by
> hardware)

... and made abundantly and absolutely clear in the spec that it is
100% without fail absolute guaranteed absolute without fail 100%
deterministic under absolute all and any circumstances as specifically
laid out in this executable pseudocode:
https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/preduce.py;hb=HEAD

> There are other possible hardware tricks, such as using
> wider-than-normal floating point for the invisible intermediate sums to
> avoid rounding errors,

the hard and inviolate rule has been set that the sub-vector
element enumeration shall without fail be 100% Precise-Interruptible
at any point in time and saveable/restorable.

an invisible wider-than-normal FP register has absolutely no
possible place to be saved and therefore has no place in any
ISA of this type.

other Vector ISAs make the conscious decision to have such
intermediary hardware and usually the penalties are that (a)
the instructions are explicit vector-sum operations and (b)
it is prohibited to interrupt the hardware in the middle of
such summations OR it must be necessary to roll-back
and re-begin the entire instruction.

none of these things i judged to be acceptable hence the
hard rule of sticking to element-based operations.  if you
want wider intermediate results use wider scalar elements.

l.