[Libre-soc-dev] Vectorised mtcr and mfcr

lkcl luke.leighton at gmail.com
Sat Aug 6 17:28:47 BST 2022

although not finalised because there is so much else to do it came up on irc "why do something stupid like vectorise mtcr and mfcr".

the answer to that question is very simple in the form of a very simple question: in a context-switch how are you supposed to save and restore 128 CR Fields?

Power ISA 3.0 only has a 32 bit CR register.  save and restore is carried out by mtcr and mfcr which then save and restore the GPR to/from the stack/context-area.

SV introduces *fifteen more* lots of 32 bit CR reg data in effect and it should be pretty obvious and natural that the most sensible way to save/restore a vector of CR regs is with the same corresponding scalar instruction itself vectorised.

i have not got round to putting this in the spec because there is so much else to do, but it should also be obvious to use the upper half of the CR reg to store CR8-CR15 Fields and go from there, thus making it 64 bit and therefore only needing to set VL to 8 and perform a vector sv.mfcr only of length 8.

it is something of a pain to have to set VL specifically for that, which was one of the motivations in early versions of SV for embedding VL into the prefix.  we ran out of space so it was removed. i do keep wondering how to bring it back.


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