[Libre-soc-dev] svp64 review and "FlexiVec" alternative

lkcl luke.leighton at gmail.com
Mon Aug 1 21:11:53 BST 2022

(re-sending, accidental toppost)


and associated test/experiment, test_preduce.py

this is the algorithm for parallel reduction. it is unusual in that
it does not include any MV operations. hardware may *make*
as many internal MV operations, use as many crossbars, use
internal in-flight regs, micro-coding, do whatever the f*** it
likes or needs to do *as long as* in the end it does NOT modify
ANY registers other than those EXACTLY as that algorithm works,
such that the results are identical.

the way that algorithm gets away with not doing MVs is that it
notes the position where a MV *would* occur, and subsequent
operations needing that value take it from the *original*
position *as if* it had been copied. whether a hardware designer
does it exactly like that or not is entirely down to them.

i mention this to hammer home that SV is more like a Software
API than it is an ISA. we define these Deterministic Schedules,
it is up to the hardware architect to implement them in any way
they see fit.

we *do not* dictate to the hardware architect how it should be
done, we *do not* prioritise or punish one microarchitecture over
another, we *do not* propagate internal microarchitecture up to
the ISA itself.


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