[Libre-soc-dev] SVP64 Vectorised add-carry => big int add
luke.leighton at gmail.com
Sun Apr 17 11:54:49 BST 2022
On April 17, 2022 9:54:14 AM UTC, Jacob Lifshay <programmerjake at gmail.com> wrote:
>afaict, that'll make the following algorithm work:
>so the inner loop in the bigint division algorithm would end up being
>> (assuming n, d, and q all fit in registers):
>> li r3, 1 # carry in for subtraction
>> mtspr CARRY, r3 # init carry spr
>> setvl loop_count
>> sv.mrsubcarry rn.v, rd.v, rq.s, rn.v
this will take a hell of a lot of convincing of the OPF ISA WG, to add, and it will need to be followed through *completely*. pseudocode, Form, justification, writeup, everything. i can't do everything on these instructions.
you need to be *really* certain that this is the best use of this space.
there is JUST enough space in EXT04 for five more 4-op multiply instructions. see Power ISA v3.1 Book III Appendix D Table 13 Sheet 7/8 on page 1357:
* bits 26-28 are set to 110
* 29-31 are the instruction, 000 001 and 011 are used,
(5 are spare, 010, 1xx)
* 21-25 which nominally are XO are actually used for RC
we had better propose a well thought through *batch* of instructions here, rather than just one.
what candidates are there, and why? bear in mind there can only be a max of 5, and OE or Rc cannot be used.
More information about the Libre-soc-dev