[Libre-soc-dev] load/store quad and svp64

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Apr 12 17:31:45 BST 2022

On Tue, Apr 12, 2022 at 5:05 PM Jacob Lifshay <programmerjake at gmail.com> wrote:

> sometimes RMW atomics are more efficient where the shared memory is rather
> than where the cpu is. part of why OpenPower needs them (iirc it doesn't
> have any).

it has LR/SC - Load-Reservation Store-Conditional but the rules are borked.
according to strict reading of the spec, the reservation is *never* cancelled
if there is no corresponding SC.

likewise, strictly, exceptions could occur in the middle, massive operations
could occur with 128-long cycle-completion (DIVs, FP ops etc.) and so on.


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