[Libre-soc-dev] microwatt verilator

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Apr 2 10:51:03 BST 2022

tobias, i'm going via https://chat.openpower.foundation/opf/channels/libre-soc
because this isn't showing up in IRC logs

> openpowerbot 8:03 AM [irc] <tplaten> I tried to run a verilator simulation over night,
> in my microwatt branch, but as expected, I did not get any uart output.
> I have heard that there is a bug that needs to be fixed in microwatt
> related to wishbone addresses.

you should absolutely in no way require waiting that long. you will
get output within seconds on the console. sdram_init.bin is
*specifically* designed to report "DRAM init" on the console
*specifically* so that you can get that early indication.

if you do not get that early indication you are completely wasting
your time proceeding further and should terminate the simulation

then when enabling VCD tracing you will be able to inspect
the simulation using gtkwave to find out what is going on.
as this includes the UART tx and rx signals and full wishbone
tracks and internal state of absolutely everything, running
for {several hours} you wasted {several hours minus 30 seconds}


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