[Libre-soc-dev] Testing Libre-SoC 0.18um test chip.

[Samuel Falvo II]

On Thu, Sep 16, 2021 at 12:42 PM Andrey Miroshnikov <
andrey at technepisteme.xyz> wrote:

> Such a tester system could probably fit into an ice40 fpga... although
> my TinyFPGA BX only has a 16Mhz clock, so from my end could only do
> "low-speed" testing.
>

The iCE40LP8K has a PLL on it which can be used to multiply clock
frequency.  I generate a VGA-compatible clock frequency on my VDC-II core
using it.  IIRC, it can potentially go up to several hundred MHz if pushed.

-- 
Samuel A. Falvo II