[Libre-soc-dev] Fwd: CVC integration into Coriolis

D. Mitch Bailey d.bailey at shuharisystem.com
Mon Nov 22 16:54:31 GMT 2021


I wrote the following response to Jean-Paul yesterday and cc'ed the 
mailing list, but it didn't show up in the digest. :(

CVC is more of an ERC tool than a logical equivalency checker, but could 
probably modify it to do at least simple LEQ checks, at first.

Excited to work together, but as I asked Jean-Paul, could you register 
my company rather than me as an individual?

D. Mitch Bailey

-------- Forwarded Message --------
Subject: 	Re: CVC integration into Coriolis
Date: 	Mon, 22 Nov 2021 13:51:27 +0900
From: 	D. Mitch Bailey <d.bailey at shuharisystem.com>
To: 	Jean-Paul.Chaput at lip6.fr
CC: 	libre-soc-dev-request at lists.libre-soc.org, 'SHR/山内さん' 
<k.yamauchi at shuharisystem.com>

Hi Jean-Paul, Marie,
> Hello Mitch,
> As Luke said, I'm now back from a short vacation. And I'm the
> main contact for the P&R and extraction, but my colleague
> Marie-Minerve is also heavily involved.
> On Fri, 2021-11-19 at 15:17 +0900, D. Mitch Bailey wrote:
> ...
>> For the past year, I've been working intermittently on a device level
>> LVS flow using magic/netgen for google/efabless/skywater and integrating
>> CVC into that design flow.
>> If Libre-SOC has a chip-level spice netlist publicly available, I'd be
>> willing to check it for errors.
> Coriolis generates netlists of the design in spice format.
> As Luke also said, the standard cells gate netlists (the only to
> contains transistors are shipped with the libraries as nsxlib).
> But there are remaining problems:
> * The netlists instanciating standard cells gates *do not*
> respect the interface ordering. This is a missing feature that
> will be added in the upcoming monts to Coriolis (read the
> spice netlists of the gates to know their order).
> For TSMC we had to "instert" a intermediate spice level
> just to reorder them. Necessary but very tedious work.
Had this same problem with the initial openlane interface. Ended up 
putting wrappers around all the standard cells, but I automated it so it 
was that much trouble. Maybe we could use the same method with Coriolis 
until the pin order is fixed. (FWIW, Openlane went with alphabetical order).
> * In the sxlib version of Libre-SOC, you will still lack the
> transistor level netlists of the SRAM blocks and PLL.
> So you may not be able to check thoses parts.
openlane uses source verilog netlists combined with standard cell spice 
netlists to do LVS at a device level using the netgen program. CVC 
requires a spice netlist and doesn't handle verilog, so what I'm doing 
now is using the extracted transistor level netlist for verification. If 
you have Calibre LVS rules, it's not too hard to create a full chip 
transistor level netlist for CVC verification.
> In Alliance/Coriolis toolchain *in real mode* we still have
> a missing link, the layout extractor. I think OpenROAD has
> a gate level one, but we would like a transistor-level one.
> I everything goes according to plan, we will be starting
> the development of one next year, with very basic features.

openlane uses magic do create a device level netlist used for LVS. 
However, netgen and magic were originally written over 30 years ago and 
have been extensively patched. I hear klayout also does extraction and 
LVS but haven't looked into it.

> Mitch, would you be interested to receive some donations from NLnet to 
> cover the integration: documentation, automated script to build the 
> tool, cover discussion with LIP6 Engineers on how to do the 
> integration itself, etc etc.
That would be fantastic! Is it possible to have the donation made to my 

D. Mitch Bailey

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