[Libre-soc-dev] Greetings

Jean-Paul Chaput Jean-Paul.Chaput at lip6.fr
Sat Nov 20 15:14:30 GMT 2021

Hello Mitch,

As Luke said, I'm now back from a short vacation. And I'm the
main contact for the P&R and extraction, but my colleague
Marie-Minerve is also heavily involved.

On Fri, 2021-11-19 at 15:17 +0900, D. Mitch Bailey wrote:
> Greetings,
> Joining the mailing list after watching Jean-Paul Chaput's and Luke 
> Leighton's presentations at Matt Venn's Opentapeout conference.
> I'm a backend layout verification/EDA developer familiar with Cadence 
> and Calibre. I've also written an open-source program that has some of 
> the capabilities of Calibre-PERC (I call it CVC - Circuit Validity 
> Checker, but unfortunately there seems to be a verilog simulator that's 
> also called CVC.). It detects static shorts, possible forward biased 
> diodes and mosfet bulk connections, Hi-Z inputs (including outputs from 
> cutoff regions), incorrect gate voltages for multipower designs, EOS 
> (electrical overstress) errors, and a few others.

  That would be very useful.

> For the past year, I've been working intermittently on a device level 
> LVS flow using magic/netgen for google/efabless/skywater and integrating 
> CVC into that design flow.
> If Libre-SOC has a chip-level spice netlist publicly available, I'd be 
> willing to check it for errors.

  Coriolis generates netlists of the design in spice format.
  As Luke also said, the standard cells gate netlists (the only to
  contains transistors are shipped with the libraries as nsxlib).
  But there are remaining problems:

  * The netlists instanciating standard cells gates *do not*
    respect the interface ordering. This is a missing feature that
    will be added in the upcoming monts to Coriolis (read the
    spice netlists of the gates to know their order).
      For TSMC we had to "instert" a intermediate spice level
    just to reorder them. Necessary but very tedious work.

  * In the sxlib version of Libre-SOC, you will still lack the
    transistor level netlists of the SRAM blocks and PLL.
      So you may not be able to check thoses parts.

  In Alliance/Coriolis toolchain *in real mode* we still have
  a missing link, the layout extractor. I think OpenROAD has
  a gate level one, but we would like a transistor-level one.
  I everything goes according to plan, we will be starting
  the development of one next year, with very basic features.


      .-.     J e a n - P a u l   C h a p u t  /  Administrateur Systeme
      /v\     Jean-Paul.Chaput at lip6.fr
    /(___)\   work: (33)              
     ^^ ^^    cell:   home:

    S U       Sorbonne Université (former UPMC)
    L I P 6   Laboratoire d'Informatique de Paris VI
    C I A N   Circuits Intégrés Analogiques & Numériques

More information about the Libre-soc-dev mailing list