[Libre-soc-dev] Fwd: [Libre-soc-bugs] [Bug 50] nmigen pinmux
luke.leighton at gmail.com
Fri Nov 12 18:01:31 GMT 2021
On November 12, 2021 12:31:19 AM UTC, lkcl <luke.leighton at gmail.com> wrote:
>i've been looking for something similar to litex (without using migen)
>written in nmigen, for some time.
>lambdasoc looks like the beginnings of such a project and has the basis
>for it, including a full working example that is capable of generating
>a standalone extremely simple BIOS.
>it also appears to support a couple of FPGA boards: ecp5 and arty a7,
>funnily enough these are what we have.
also needed is JTAG Boundary Scan. so although auto-generating a SoC file is pretty straightforward, it is no good (for us) if that SoC does not support JTAG Boundary.
this means that the ENTIRE pinset has to, instead of being directly connected to "pins", where the assumption is that those "pins" will come out in verilog at the top level and you wire them direct to the ASIC Corona (where all the IOPads are), you must first *reroute* them - all of them - through the JTAG Boundary Scan instance.
what in practical terms that means is that we have to override the nmigen Platform class with "rerouting" of the functions that create the Signals for inputs, outputs, and in/out/oe-ers.
where normally the Platform would request the addition of an input, to be set as an external toplevel verilog Signal, instead that input must be connected to JTAG... and the *JTAG* muxed correspondingly-named Signal is returned as the external toplevel Signal instead.
i do wish i had investigated how to this in nmigen earlier. the corresponding litex code, in migen, was absolute hell to write.
anyway, it is actually pretty straightforward. i will create corresponding bugreports.
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