[Libre-soc-dev] daily kan-ban update 10nov2021

lkcl luke.leighton at gmail.com
Wed Nov 10 18:18:10 GMT 2021

On November 10, 2021 6:07:18 PM UTC, Tobias Platen <libre-soc at platen-software.de> wrote:
>wrote case_5_ldst_exception, where I saw that the "problem" state MSR
>is not passed to LoadStore1. I guess that this is a bug in the core or
>in the issuer.

no, neither: remember, we have never added any kind of exception handling, virtual memory, anything, to any data structures, it is entirely missing, not a bug, because it was intentional not to handle exceptions at all for the first ASIC.

you've identified a location where in the ripple-effect propagation of exceptions and privileged state needed, MSR.PR is simply missing.

it will need adding to the LDST record, first. ldst multicompunit:

 103 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset


  23                   ('msr', 64), # TODO: a lot less bits.  only need PR

ok! so that is already there.  but it is missing from pipe_data.py

hmmm trap has msr:


ok i will just add that, gimme 1 sec


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