[Libre-soc-dev] NGI POINTER gigabit ethernet router ASIC roadmap

lkcl luke.leighton at gmail.com
Mon Nov 1 13:43:44 GMT 2021

On November 1, 2021 12:00:38 PM UTC, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> wrote:

>Yes. I would just need an updated netlist with the blackbox done the
>way as a SRAM. And a rough idea about it's dimensions and external pins
>  placement.
> Another question: are the PHY on the chip or will they be "externally"
>  connected (i.e. should I make blackboxes for them too) ?

we will use external digital-only PHYs, the only thing being the signals are DDR.

USB2 ULPI PHY, all digital signals, 60 mhz clock:

RGMII Gigabit Ethernet PHY, 25/125mhz clock, DDR signalling:

in both cases it is the *PHY* that generates the incoming clock used by the ASIC, pretty much exactly as is the case with JTAG, in fact the exact same techniques as c4m-jtag HDL can be used: to drive the ASIC PHY by the incoming clock, on both rising and falling edge, for both Tx and Rx.

this does mean however we will have:

* main pll_clk going to PLL to generate sys_clk
* jtag_tck (25 khz max)
* eth_clk (125 mhz max)  there will be FIVE of these
* usb_clk (60 mhz max)    there will be TWO of these

i realise that is a hell of a lot of clock trees :)

the most important thing to observe here is, though: no internal PLL extra frequencies needed, the existing (one) PLL by Professor Galayko is perfectly fine.

i am surprised that the USB3300 is not DDR, and that it is 8-bit signals (that is UTMI, not ULPI). i thought that ULPI was supposed to be DDR only 4-bit buses, perhaps some of the Texas Instruments ULPI PHYs i have seen are DDR and 4-bit

also, very important: the USB3300 *must* supply its own 1.8v VREF for the Digital IO.  i realise that this means 3 Power Rails.  if that is a problem then we find a different PHY *or* on the PCB have a Level-Shifter IO IC, 60 mhz is not difficult to do.

the RTL8211 on the other hand, this can be given an External VREF for IO and it works fine at 3.3v.


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