[Libre-soc-dev] NGI POINTER gigabit ethernet router ASIC roadmap
Jean-Paul.Chaput at lip6.fr
Mon Nov 1 11:42:09 GMT 2021
On Mon, 2021-11-01 at 11:11 +0000, lkcl wrote:
> (Staf, summary, i know you are busy with deadlines: no real change here for you)
> there is not much time to get a lot done and not enough full time committed people to
> do it. therefore some tough decisions need to be made to limit what goes into the
> we have 5-6 months to get the entire HDL ready and simulated for the gigabit router
> ASIC. layout will have to start around month 4-5 into that, with preliminary
> HDL. total available time including the MPW: ELEVEN months.
> Jean-Paul: when we did DFFs/SFFs for regfiles they were distributed extremely optimally
> right the way through the layout. the actual ALUs were distributed as well, and it was
> both very cool and well routed.
> but, for fixed size (compact) regfiles that are basically SRAM blocks, this is a very
> different scenario, and having those SRAMs (regfiles) up in the top row is going to
> cause huge routing congestion. something to think about.
Yes. It's floorplaning work. About the placement of SRAM (or *any* sizeable
macro-block), they must be put on *any* side of the chip so the regular clock
tree spreading from the center of the design is not hampered.
The very first step is to have an idea of the relative size of all the
macro-blocks of the chip, and the overall number of standard cell gates.
Then I can envision both floorplaning and any clock-tree modifications
that the clock tree generator may need (this is coupled).
I would like to start that exploratory work as soon as possible and not
wait for a provisional realistic HDL to be ready. So would it be possible
to have the size & numbers of macro-blocks (both SRAM & analogs) so I can
create abstracts, and a "fake" design that instantiate them and has a similar
number of gates after logical synthesis?
.-. J e a n - P a u l C h a p u t / Administrateur Systeme
/v\ Jean-Paul.Chaput at lip6.fr
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S U Sorbonne Université (former UPMC)
L I P 6 Laboratoire d'Informatique de Paris VI
C I A N Circuits Intégrés Analogiques & Numériques
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