[Libre-soc-dev] PLL integration

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu May 27 13:09:01 BST 2021

i know what it is: it's that there's no temporary / intermediary signal.  i
connect the PLL wires *directly* between two modules, and this is confusing

i can fix it by creating an intermediate wire in test_issuer.


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