[Libre-soc-dev] PLL integration
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu May 27 12:31:01 BST 2021
On Thu, May 27, 2021 at 12:01 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
> We have to check the blif file to see if the error is due to
> Yosys or blif2vst. If it's on my side I will fix it. If not,
> I may force the signal direction (to build the clock tree I
> need to known where is the driver).
puzzlingly, the spblock_512xxx blackbox ends up entirely with "linkage" in
its VST file.
> Small other point : to be similar to what I do with the TSMC
> variant, the "pll" black box should be renamed into "cmpt_pll".
> But it's optional I manually made the correction in the relevant
> Verilog files (not commited).
mmmm... *thinks*... that's because it's a blackbox, and blackboxes
are excluded from the rename to "cmpt_" prefix, isn't it.
can you please commit the soclayout9/tsmc_018 changes you have so that
i can see what's going on, and keep in sync?
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