[Libre-soc-dev] PLL integration

[Luke Kenneth Casson Leighton]

On Wed, May 26, 2021 at 2:36 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
wrote:


>   repositories of soclayout (the old for 1. and the freshly cloned
>   for 2). So I can port one by one with checking every changes I
>   made in soclayout.
>

makes sense


>   In experiment9, we now also have three flavors :
>     1. experiment9/  : classic symbolic with Nsxlib.
>

this is for me to "track" what you are doing.

    2. experiment9/freepdk_c4m45/ : FlexLib on FreePDK45.
>

ignore this one for now, i have mostly what i need in nsxlib one.

800 Used module:                         \DIV_ERROR: Module `test_issuer'
> referenced in module `ls180'
>                                                      in cell `test_issuer'
> does not have a port named
>                                                      'sram4k_3_wb__err'.
>

i fixed that 3 days ago.  it's not actually _used_, but...  hang on this
might be the cause:

diff --git a/experiments9/tsmc_c018/Makefile
b/experiments9/tsmc_c018/Makefile
index bac3d68..a5ad72a 100755
--- a/experiments9/tsmc_c018/Makefile
+++ b/experiments9/tsmc_c018/Makefile
@@ -15,7 +15,7 @@
                 VST_FLAGS = --vst-uniquify-uppercase

                  #NETLISTS = $(shell cat cells.lst)
-                 NETLISTS = ls180
+                 NETLISTS = ls180 libresoc
 #            YOSYS_FLATTEN = $(shell cat flatten.lst)


  What am I missing ?
>

don't know.  try git pull now
https://git.libre-soc.org/?p=soclayout.git;a=commit;h=8e47fc30397facfa995f77835d9e8583c8874357

in the meantime i will remove that signal, it isn't used anyway.

l.