[Libre-soc-dev] PLL integration

[Marie-Minerve Louerat]

Le 26/05/2021 à 15:36, Jean-Paul Chaput a écrit :
> On Wed, 2021-05-26 at 11:14 +0100, Luke Kenneth Casson Leighton wrote:
>> JP you definitely need to stay up-to-date on latest soclayout. currently
>>
>> https://git.libre-soc.org/?p=soclayout.git;a=commit;h=689f3552a1d8198759581dadf0bc71227076fcbc
>
>    I am. I even made a fresh "git clone" to be sure I have the up to date
>    pristine contents.
>      It very difficult (verging on impossible) to develop/debug Coriolis,
>    or any tool for that matter, if the test cases (in our case, netlists)
>    moves under my feets ever so slightly.
>      So I progress by leaps between Coriolis and soclayout :
>      1. All others things constants, add features & debug Coriolis.
>      2. At Coriolis constant, update to the latest soclayout.
>      And when switching between 1 --> 2 I keep two seperate git
>    repositories of soclayout (the old for 1. and the freshly cloned
>    for 2). So I can port one by one with checking every changes I
>    made in soclayout.
>
>    In experiment9, we now also have three flavors :
>      1. experiment9/  : classic symbolic with Nsxlib.
>      2. experiment9/freepdk_c4m45/ : FlexLib on FreePDK45.
>      3. experiment9/tsmc_c180/ : Flexlib on TSMC 180nm.
>
>    I have used Yosys 0.9 git 049e3abf9baf795e69b9ecb9c4f19de6131f8418.
>
>    And got :
>      1. wrappll wrap_pll_clk_sel_i only "half connected" (bit 1 stuck
>         to zero in the BLIF file).
>      3. Exact same error as for 1.
>      2. Yosys do not complete :
>
>   52  Yosys 0.9+4008 (git sha1 UNKNOWN, gcc 4.8.5 -fPIC -Os)
>   53
>   54 1. Executing Verilog-2005 frontend: pll.v
>   55 Parsing Verilog input from `pll.v' to AST representation.
>   56 Generating RTLIL representation for module `\pll'.
>   57 Successfully finished Verilog frontend.
>   58
>   59 2. Executing Verilog-2005 frontend: spblock_512w64b8w.v
>   60 Parsing Verilog input from `spblock_512w64b8w.v' to AST representation.
>   61 Generating RTLIL representation for module `\spblock_512w64b8w'.
>   62 Successfully finished Verilog frontend.
>   63
>   64 3. Executing Verilog-2005 frontend: ls180.v
>   65 Parsing Verilog input from `ls180.v' to AST representation.
>   66 Generating RTLIL representation for module `\ls180'.
>
>   ...
> 794 Used module:                 \dec_DIV
> 795 Used module:                     \dec_rc$154
> 796 Used module:                     \dec_oe$155
> 797 Used module:                     \dec_bi$157
> 798 Used module:                     \dec_ai$156
> 799 Used module:                     \dec$153
> 800 Used module:                         \DIV_ERROR: Module `test_issuer' referenced in module `ls180'
>                                                       in cell `test_issuer' does not have a port named
>                                                       'sram4k_3_wb__err'.
>
>
>    What am I missing ?

I recall our previous request to be able to perform the verification:


> Therefore, on :
>
> - 4 May, we request that the design is stabilized, thus:
>
>   * select Verilog OR RTLIL as the input behavioral description
>     language for YOSYS
>   * validate the description after YOSIS synthesis with simulation
>     patterns (+ RAM, + JTAG)
>   * freeze the behavioral description (in the selected format)
>   * freeze Yosys version
>   * commit the above selection in the "soclayout" git of LibreSoC with
>     a dedicated tag,
>   * OR commit the above selection in the "soclayout" git of LibreSoC
>     as a branch and a tag
>
>

>
>
>> then see experiments9/build_full_4ksram.sh
>>
>> https://git.libre-soc.org/?p=soclayout.git;a=blob;f=experiments9/build_full_4ksram.sh;hb=HEAD
>>
>> note that it now uses VERILOG not ilang/rtlil
>>
>> corresponding Makefile also slightly updated.
>>
>> _______________________________________________
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>> Libre-soc-dev at lists.libre-soc.org
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-- 
Marie-Minerve Louerat
Equipe CIAN du Laboratoire LIP6
Sorbonne Université, CNRS
Campus Pierre et Marie Curie
4 Place Jussieu, 75005 Paris, France
+33 1 44 27 71 08
marie-minerve.louerat at lip6.fr