[Libre-soc-dev] PLL integration

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue May 25 10:51:36 BST 2021

On Tue, May 25, 2021 at 10:49 AM <dimitri.galayko at lip6.fr> wrote:

> Dear all,
> Sorry, I have overlooked this point.
> Do you want me to rename the « out » signal in the provided PLL design ?
> It is easy to do.

i would prefer it, however let us wait to see from Jean-Paul if it is
necessary / if he approves: ironically it may be extra work for him to
*remove* a workaround he has already added :)


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