[Libre-soc-dev] SVP64 sv.stfsu

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed May 19 14:44:39 BST 2021

On Wed, May 19, 2021 at 11:47 AM Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> also this is the first time doing a Vectorised store-with-update and
> i just remembered that we need to ensure that *both* the RA-as-input
> *and* RA-as-output need to be marked as Vectors, and i have a
> suspicion (based on tests so far) that that's not the case.

sorted.  the SVP64 Assembler parser/decoder was not able to cope with
RA being both a source and a destination in the SVP64 EXTRA2/3

i'll now document the test because it's quite complex / involved, even
it's only 3 instructions.

        lst = SVP64Asm(["sv.lfsx 0.v, 0, 4.v",
                        "sv.stfsu 0.v, 16(4.v)",
                        "sv.lfs 3.v, 0(4.v)",

there's quite a lot going on here: in particular, the sv.stfsu *overwrites*
and GPR 5 with *two* Effective Address calculations (one for each element)
which the following sv.lfs can easily pick up.


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