[Libre-soc-dev] video assembler
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri May 14 16:58:43 BST 2021
On Fri, May 14, 2021 at 2:42 PM Lauri Kasanen <cand at gmx.com> wrote:
> > also what is useful is, once an algorithm has been written, is to see if
> > there are better instructions or less instructions that could be used *or
> > added to the ISA*, based on an assumption that the "best" hardware
> > implementation will ensure 100% throughput without stalls.
> Amdahl's law, different approaches to a problem, interleaving
> when no hw can rearrange code too far, etc etc. These all apply to SV
thinking that through... even there, we plan to use a massive cyclic
shift register (a conveyor belt) internally onto which "wrong" sized
operands are dropped, converted, and spat out to the right "lane" at
the right width. this *should* only introduce latency, where
increasing the number of parallel Out-of-Order Function Units should
allow sufficient slack.
however if that becomes too much to handle then we have to back it
down: it *may* be the case that things such as performing an extra
MV-with-saturate and operate at a wider bitwidth or something is
easier: these kinds of things we will find out as we go along.
> I do get what you're trying to say.
sorry it was a bit long.
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