[Libre-soc-dev] Fwd: [Git][vlsi-eda/coriolis][devel] 6 commits: Fix unitialized stat structure in Vlsisapd, Path::mode() (valgrind).
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue May 11 16:14:21 BST 2021
---------- Forwarded message ---------
From: Jean-Paul Chaput (@jpc) <gitlab at gitlab.lip6.fr>
Date: Tue, May 11, 2021 at 1:35 PM
Subject: [Git][vlsi-eda/coriolis][devel] 6 commits: Fix unitialized
stat structure in Vlsisapd, Path::mode() (valgrind).
To: <coriolis-cvs at soc.lip6.fr>
Jean-Paul Chaput pushed to branch devel at Coriolis VLSI EDA / Coriolis
by Jean-Paul Chaput at 2021-05-11T14:30:38+02:00
Create clusters for wire only chunks and add diodes if they are too long.
Protecting clusters of sinks is not enough. There can be very long
wires that far exceed the protection capacity of one diode. Instead
of putting a bunch of diodes near the sinks, we choose to put them
regularly along the interconncting wires.
With this approach we are down to 7 antenna violations on LibreSOC
LS180 test chip.
This will get less good results on arlet6502 & ao6800 because of the
core being a long way from the I/O pads. Should create jumpers on thoses,
but it is for later.
15 changed files:
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