[Libre-soc-dev] microwatt / libresoc dcache
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon May 10 13:42:04 BST 2021
On Monday, May 10, 2021, Benjamin Herrenschmidt <benh at kernel.crashing.org>
> 48 bits of address-compares? 48x XOR gates (10 gates per XOR), times
> > 64, that's 31,000 gates! woo!
> Euh... no, it's a set associative TLB, not a CAM at all.
tck, tck.... ah yes
ok. so the LSBs are treated as the lookup, meaning a standard 1R1W
SRAM/BRAM could be used. and that should be single cycle, no problem.
which makes me curious as to what the heck is going on if timing there is
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