[Libre-soc-dev] daily kan-ban update 04may2021
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue May 4 20:10:20 BST 2021
On Tuesday, May 4, 2021, Tobias Platen <libre-soc at platen-software.de> wrote:
> On Tue, 2021-05-04 at 19:27 +0100, Luke Kenneth Casson Leighton wrote:
> > ---
> > crowd-funded eco-conscious hardware:
> > https://www.crowdsupply.com/eoma68
> > On Tue, May 4, 2021 at 7:18 PM Tobias Platen
> > <libre-soc at platen-software.de> wrote:
> > > Yes I have read all emails I have got. First I had a look to
> > > mmu/fsm.py
> > > line 351 to 366. spr1_o.data is set to spr and a_i is ignored. They
> > > both need to be passed to the SPR regfile. spr1_i.data is still
> > > unused.
> > should be exactly the same as spr main_stage.py
> > https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/
> I saw, there are fast SPRs first and then slow SPRs TODO. spr1_o and
> spr1_i are used for the slow ones.
yes. DSISR etc are not on the list of Fast SPRs, these include SRR0, DEC,
LR, CTR etc.
there already exists a slow spr read/write port in regspecs:
no need to change anything there.
spr1 input should already be accessible as self.i.spr1 and likewise spr1
output as self.o.spr1.
remember that a regspec declared as an output is automatically a Record
which has "data" and "ok".
you MUST set the "ok" field to 1 to get it to write.
comb += self.o.spr1.ok.eq(1)
failure to do that *will* result in a lock-up of the CompUnit.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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