[Libre-soc-dev] dcache and mmu linked up

Tobias Platen libre-soc at platen-software.de
Mon May 3 18:43:48 BST 2021

On Mon, 2021-05-03 at 18:02 +0100, Luke Kenneth Casson Leighton wrote:
> On Sunday, May 2, 2021, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
> > one test needed is to disable the cache entirely (nc=1) so as to
> > eliminate
> > it as a possible source of data corruption.
> > 
> > litexbios is currently calculating the wrong value.
> > 
>  the reason turned out to be an overlap between load and store, when
> printing out the bios intro.  the LOAD (to read the character)
> overlapped
> with STORE (writing to UART) which resulted in the bios messages
> being
> corrupted.
> all sorted, which means that physical dcache read/write is working.
> again there are no errors yet.  next stage is to try enabling MMU
> mode.
> this *will* need error handling.
I have been thinking about error handling long time ago. Setting the
DSISR and DAR registers needs to be done, I had looked into the
microwatt source code to find out how it is done there.
> l.

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