[Libre-soc-dev] fighting litex and yosys for pin mapping
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Mar 28 16:49:30 BST 2021
PLEASE NOTE - to get the gate count down for the ls180 tape-out i've had to
make some rather invasive changes to the size of the SPR regfile.
as that is driven by an enum (used to be Enum SPR) covered by SPRMap (which
converts from OpenPOWER9 SPR numbers to internal) that had to be changed to
a *compile-time-selectable* Enum.
in theory this should not cause problems (not be noticed), i've re-run the
full test_issuer.py unit test and it's fine.
On Sun, Mar 28, 2021 at 1:30 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> i've spent the past week dealing with litex and yosys to get the JTAG
> boundary scan connected up.
> litex provides absolutely no help whatsoever in determining the direction
> of wires: it is purely a naive "generator of verilog by outputting text
> fragments that happen to be in verilog".
> ordinarily, yosys would be useful to help determine whether those
> directions are correct... except that there are also *bugs in yosys* which
> leave it unable in all cases to correctly determine port direction.
> so it's been 4 days to track down the problem (hidden by another problem
> that had to be tracked down) followed by 3 days iterating solutions.
> i've finally got something that might be correct.
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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