[Libre-soc-dev] [RFC] svp64 "source zeroing" makes no sense

[Luke Kenneth Casson Leighton]

On Sunday, March 21, 2021, Richard Wilbur <richard.wilbur at gmail.com> wrote:

> On Sun, Mar 21, 2021 at 4:13 PM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> >
> > so on each iteration, here are the four options, assume predicates on
> both
> > src and dest:
> >
> > * no zeroing.  this is a back-to-back VREDUCE-VEXPAND
> >
> > *  source-predicate zeroing this is a VREDUCE with zeros inserted into
> the
> > output
>
> I guess it escapes me why this is called source predicate zeroing if
> it only affects the output.


i know.  odd, isn't it.  the clue is in

       if (src_zeroing and ((1<<srcstep) & srcmask) == 0) or
          (dest_zeroing and ((1<<dststep) & srcmask) == 0)):
            result = 0

it's not

       if (dest_zeroing and ((1<<srcstep) & srcmask) == 0) or
          (dest_zeroing and ((1<<dststep) & srcmask) == 0)):
            result = 0

it's not

       if (src_zeroing and ((1<<srcstep) & srcmask) == 0) or
          (src_zeroing and ((1<<dststep) & srcmask) == 0)):
            result = 0

it's

       if (src_zeroing and ((1<<srcstep) & srcmask) == 0) or
          (dest_zeroing and ((1<<dststep) & srcmask) == 0)):
            result = 0




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